1. Technical Field
The present invention relates to semiconductor processing, and more particularly to methods and devices that provide a reference plane for gate height control and planarity.
2. Description of the Related Art
Dummy gate height for fin field effect transistor (FinFET) technologies has not scaled directly from node to node. This often leads to problems including gate structures that are too short. A minimum height is needed to ensure that there is sufficient height for all subtractive processes and their tolerances.